1. Field of the Invention
The present invention pertains to a reconfigurable array of test structures and a method for testing test structures employing a reconfigurable array of test structures.
2. Discussion of the Background
In semiconductor manufacturing, semiconductor devices are not typically constructed individually, but rather in multiples, frequently large multiples. For example, in the manufacture of a semiconductor device, several hundred or more devices will be prepared simultaneously on a single substrate. This substrate or sheet will later be die-cut to provide the individual semiconductor devices. During the step-wise assembly of the semiconductor devices, it is advantageous to test, occasionally more than once, portions of the partially assembled or the completely assembled semiconductor devices so as to monitor the manufacturing process and to identify the malfunctioning devices.
Further, in semiconductor manufacturing, there is significant economic pressure to reduce the costs of manufacturing. Thus, there is a greatly increased demand for maximizing the number of semiconductor devices that can be assembled on a given substrate. Unfortunately, this demand has made it increasingly difficult to justify the space allocated for parameter test structures on the semiconductor device, which occupy a significant amount of valuable substrate area and do not serve any further purpose after the test measurements have been performed. These parameter test structures represent underutilized or "dead" space on the semiconductor device, which space, if properly utilized could either provide additional semiconductor devices, for example, memory chips, PAL, and CPU; or optimize the die layout on the silicon wafer.
Conventional parameter test structures are very small, but the probe pads through which the testing equipment access these structures, must be quite large so as to accommodate inaccurate alignment or minor misalignment of the testing equipment and to ensure satisfactory electrical contacts. Accordingly, conventional manufacture of test structures results in a significant amount of substrate area that is not incorporated into a semiconductor device and which does not serve any purpose after the manufacturing process.
To address this wasted substrate area, various approaches have been pursued in an attempt to increase the area of utilized substrate. These approaches have included decreasing the size of the probe pads, placing the parameter test structure outside the scribe lines of the die, and allocating portions of the die for testing purposes only. These approaches are described in U.S. Pat. No. 4,014,037 to Matsushita et al.; U.S. Pat. No. 4,041,399 to Tsuda; U.S. Pat. No. 4,063,275 to Matsushita et al.; U.S. Pat. No. 4,302,763 to Ohuchi et al.; U.S. Pat. No. 4,176,372 to Matsushita et al.; U.S. Pat. No. 4,198,283 to Class et al.; U.S. Pat. No. 4,302,763 to Ohuchi et al.; U.S. Pat. No. 4,771,009 to Ueki; U.S. Pat. No. 5,068,697 to Noda et al.; U.S. Pat. No. 5,102,819 to Matsushita et al.; U.S. Pat. No. 5,126,028 to Hurwitt et al.; U.S. Pat. No. 5,243,213 to Miyazawa et al.; U.S. Pat. No. 5,334,555 to Sugiyama et al.; U.S. Pat. No. 5,342,652 to Foster et al.; U.S. Pat. No. 5,349,456 to Iwanaga et al.; U.S. Pat. No. 5,360,524 to Hendel et al.; and U.S. Pat. No. 5,377,030 to Suzuki et al. Unfortunately, these approaches have achieved only small increases, if any, in the utilized area of the substrate. Accordingly, there remains a need for a method of semiconductor manufacture which results in a significant increase in the utilized area of semiconductor substrate.